1. Field of the Invention
This invention relates to computer system input/output (I/O) and, more particularly, to I/O nodes including integrated I/O functionality.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many bus systems suffer from several drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. Examples of a shared bus used by I/O devices are a peripheral component interconnect (PCI) bus and an extended peripheral component interconnect (PCI-X) bus.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a xe2x80x9cnodexe2x80x9d is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a xe2x80x9cpacketxe2x80x9d is a communication between two nodes: an initiating or xe2x80x9csourcexe2x80x9d node which transmits the packet and a destination or xe2x80x9ctargetxe2x80x9d node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Additionally, there are systems that use a combination of packet-based communications and bus-based communications. For example, a system may connect to a PCI-X bus and a graphics bus such as AGP. The PCI-X bus may be connected to a packet bus interface that may then translate PCI-X bus transactions into packet transactions for transmission on a packet bus. Likewise the graphics bus may be connected to an AGP interface that may translate AGP transactions into packet transactions. Each interface may communicate with a host bridge associated with one of the processors or in some cases to another peripheral device.
Since transactions associated with many peripheral buses have ordering rules, many of the packet bus interfaces may have arbitration rules to ensure that the peripheral transactions do not become stalled. I/O devices which use communication protocols such as Ethernet or Infiniband(trademark) may be connected to the system via card slots on buses such as the PCI-X bus and may thus be constrained by the arbitration rules associated with the PCI-X bus. In addition, those I/O devices may have bandwidth requirements that may cause other devices connected to the PCI-X bus to be unintentionally starved or vice versa.
In some systems, the processor connects to the system I/O using one or more integrated circuit chips that may be part of a chipset. In some cases, an I/O node may be manufactured on an integrated circuit chip that may be dedicated to one type of peripheral bus, such as the PCI-X bus. Thus, if an I/O device as described above were connected to the I/O node through such peripheral bus, there may be undesirable results.
Various embodiments of an I/O node including an integrated I/O interface are disclosed. In one embodiment, an input/output node for a computer system that is implemented on an integrated circuit chip includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit.
The first transceiver unit may be configured to receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may be coupled to receive and transmit packet transactions on a second link of the packet bus. The packet tunnel is coupled to convey selected packet transactions between the first transceiver unit and the second transceiver unit. The bridge unit is coupled to receive particular packet transactions from the first transceiver and may be configured to transmit transactions corresponding to the particular packet transactions upon a peripheral bus, such as for example, a PCI-X bus. The I/O interface unit is coupled to receive additional packet transactions from the first transceiver and may be configured to transmit transactions corresponding to the additional packet transactions upon an I/O link, such as an Ethernet link, for example.
In one particular implementation, the I/O node may further include a control unit coupled to control the conveyance of the selected packet transactions, the particular packet transactions and the additional packet transactions between the first transceiver and the second transceiver, between the first transceiver and the bridge unit and between the first transceiver and the I/O interface unit, respectively.
In one particular implementation, the I/O interface unit may be further configured to receive I/O transactions on the I/O link and to transmit transactions corresponding to the I/O transactions to the first transceiver unit.
In another implementation, the bridge unit may be further configured to receive peripheral transactions from the peripheral bus and to transmit transactions corresponding to the peripheral transactions to the first transceiver unit.
In yet another implementation, the control unit may be further configured to establish an arbitration priority between the first and second transceiver units, the I/O interface unit and the bridge unit.